1. Field of the Invention
The present invention is related to a semiconductor package in which a semiconductor die is disposed between upper and lower plate members having outside dimensions of an S08 semiconductor package. The drain of an enhancement mode Junction Field Effect Transistor(JFET) die is electrically coupled to the lower plate member, while the JFET source is coupled to a leadframe via an upper plate member and the JFET gate is electrically coupled to the leadframe via a conductive ribbon.
2. Related Art
With reference to FIG. 1, a semiconductor package 100 according to the prior art is shown. The semiconductor package 100 includes a bottom plate portion 105 and terminals 120, 121. A semiconductor die 130 is disposed on top of the bottom plate portion 105 and fastened thereto, typically using an epoxy material. The semiconductor die 130 includes a metalized region 135 (typically aluminum) defining a connection area for a top surface of the semiconductor die 130. Portions of the terminals 120, 121, bottom plate portion 105, and semiconductor die 130 are encapsulated in a housing 140, typically formed from a moldable material. In order to obtain an electrical connection between the metalized region 135 and the terminal(s) 121, one or more wires 122 are ultrasonically bonded at one end 123 to the metalized region 135 and at a distal end 124 to the terminal 121. One surface of the semiconductor die 130 is coupled to the bottom plate 105 by means of a conductive material 106.
FIG. 2 shows another semiconductor package 200 of the prior art. In order to electrically connect the metalized region 135 with the terminal 121, one or more wires 131 are stitch bonded at locations 132, thereby providing additional paths for current to flow from the semiconductor die 130 to the terminal 121. This marginally reduces the resistance of the current path from the semiconductor die 130 to the terminal 121.
It is desirable to significantly reduce the resistance and inductance of current paths through a power semiconductor package in order to ensure optimum performance of the semiconductor device. Unfortunately, the semiconductor packages of the prior art do not fully achieve this objective because, among other things, the distance D shown in FIG. 1 between one area of the metalized region 135 and the end 123 of the wires 122 increases the resistance of the current path from the metalized region 135 to the terminal 121. This problem is exacerbated when the thickness of the metalized region 135 is relatively small (typically, the thickness is approximately 4 to 8 microns). The relatively thin metalized region 135 in combination with the distance D and the cross sectional profile of the wire bond 122 results in a relatively high resistance and inductance for the current path therethrough.
In some packages (for example S08 packages) the distance D is approximately 80 to 100 mils resulting in a resistance of between about 0.79 and 1.58 mohms for the metalized region 135. The diameters of the wires 122, 131 are approximately 2 mils yielding resistances of about 1.05 mohms (when 14 wires are used). With terminal and epoxy resistances aggregating to about 0.307 mohms, such packages exhibit total resistances of between about 2.14 to 2.93 mohms. The resulting package thermal resistance, RJA, can reach 62.5 degrees Centigrade per Watt.
When the semiconductor package 100 includes, for example, an FET semiconductor die 130, the resistance caused by the distance D and the relatively small diameter of the wires 122, 131 adds to the overall resistance of the FET. Indeed, when die 130 is a FET die, the terminals 120 are typically coupled to the drain of the FET while the terminals 121 are coupled to the source of the FET via one or more wire bonds 122. As ON resistances of FET dies become smaller and smaller, the resistance caused by the distance D and the wire bonds 122, 131 become a larger and larger portion of the overall resistance from one terminal 120 to another terminal 121. Of course, the high frequency performance of a semiconductor device, like an FET, is significantly affected by the resistance and inductance from terminal to terminal through the device.
Some prior art packages have incorporated a large metal strap to obtain an electrical connection between the metalized region 135 and terminal 121. Unfortunately, this technique has only been possible in large semiconductor packages having relatively simple surface structures, such as bipolar junction transistors, diodes, and thyristors. Further, the metal straps were not practical in small outline packages (such as S08, surface mount dual in line packages). The use of a large metal strap in a gated device, such as an FET, has not heretofore been achieved because such devices have relatively complex surface structures. In particular, gated devices typically include a gate runner (or bus), disposed on the surface of the semiconductor die, which traverses the surface such that gate potential is distributed over the surface of the die. Consequently, disposing a large metal strap over the surface of the die has been problematic because the gate runner restricts access to the die surface and could be shorted to the metal strap. Thus, the use of metal straps in gated semiconductor devices has been prohibitive.
Accordingly, there is a need in the art for a new semiconductor package which overcomes the deficiencies in the prior art semiconductor packages by, among other things, reducing the resistances and inductances of the current paths through gated devices such as MOSFETs and JFETs.
Accordingly, what is needed is a more generally applicable system that will overcome deficiencies of the prior art. One embodiment of the present invention includes a semiconductor package that incorporates a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power enhancement mode JFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.